At least one type of prior flash erasable and electrically programmable read-only memory ("flash EPROM") uses memory cells that include electrically isolated gates, which are referred to as floating gates. Information is stored in the memory cells in the form of charge on the floating gates. FIG. 1 illustrates the structure of one memory cell 10 used in one type of prior flash EPROM. Memory cell 10 includes a drain region 13 and a source region 14 in a substrate 15. Source region 14 and drain region 13 are asymmetrically doped with an arsenic dopant and source region 14 is additionally doped with a phosphorous dopant. A polysilicon floating gate 12 is generally disposed above and between these regions and insulated from these regions by an insulating layer 16. Floating gate 12 at the completion of processing is completely surrounded by insulating layers and hence electrically floats. A second gate (i.e., a control gate) 11 is disposed above floating gate 12 that is fabricated from a second layer of polysilicon. A second insulating layer 17 separates floating gate 12 from control gate 11.
The memory cells of that prior flash EPROM are programmed by hot electron injection. Each of the memory cells is a MOS transistor having a floating gate. Energetic electrons are created in the silicon channel. The electrons are attracted and captured into the floating gate, thus altering the threshold voltage of that memory cell. The threshold voltage is the minimum amount of voltage that must be applied to the control gate before the memory cell is turned "on" to permit conduction between its source and drain region. The threshold voltage characteristic of the memory cell is controlled by the amount of charge that is retained on the floating gate of the memory cell. Such a cell is now said to be "programmed." The programming characteristics of a cell are exponential with respect to time.
Memory cell 10 is programmed (i.e., negatively charging the floating gate) by coupling control gate 11 to a gate programming potential of approximately +12 volts, drain region 13 to a drain programming potential of approximately +7 volts, and source region 14 to ground. Under these conditions, channel hot electron injection occurs through oxide layer 16. The electrons deposited on floating gate 12 of memory cell 10 causes the threshold voltage of memory cell 10 to rise. Memory cell 10 is now programmed to have a programmed threshold voltage V.sub.TP.
To erase cell 10, drain region 13 is floated, control gate 11 is grounded and an erasure potential of approximately +12 volts is applied to source region 14. Under these conditions, charge is tunneled from floating gate 12 to source region 14. This removes the electrons deposited on floating gate 12 of memory cell 10, causing the threshold voltage of memory cell 10 to decrease. Memory cell 10 is now erased to have an erased threshold voltage V.sub.TE.
To read cell 10, a positive read potential less than that which would cause charge to transfer onto floating gate 12 is applied to control gate 11 (e.g., 5 volts) and a potential (e.g., 1 volt) is applied to drain region 13. Current through the device is sensed to determine if floating gate 12 is or is not negatively charged.
The speed at which memory cell 10 is programmed largely depends on the programming ability of cell 10 and the programming voltages applied to cell 10. The programming ability of cell 10 affects the programmed threshold voltage V.sub.TP of the cell. One of the factors that affects the programming ability of cell 10 is the effective channel length L.sub.eff of the cell. Another factor is the peripheral circuitry that performs the programming operation to cell 10. For purposes of simplicity, the effective channel length L.sub.eff of the cell can be considered as quantifying the process variations and other variations. For example, lithographic, etching, and diffusion processes all contribute to the process variations. FIG. 2A illustrates the relationship of the threshold voltage V.sub.t of memory cell 10 during programming with respect to the programming time and the effective channel length L.sub.eff.
In FIG. 2A, curve 21 is an example of the relationship between the threshold voltage and the programming time of cell 10 when the effective channel length L.sub.eff of cell 10 is 0.3 .mu.m. Curve 22 indicates the relationship between the threshold voltage and programming time of cell 10 when the effective channel length L.sub.eff of cell 10 is 0.4 .mu.m. As can be seen from FIG. 2A, if the effective channel length L.sub.eff is relatively longer, the programming time for cell 10 to reach the same threshold voltage will accordingly be longer when the programming voltages applied to cell 10 remain unchanged.
One disadvantage of a prior flash EPROM is that there are variations in effective channel length from cell to cell and variations in mean effective channel length for the flash EPROM from die-to-die and from fabrication lot to fabrication lot. In other words, a flash EPROM produced in one fabrication lot would, for example, typically have a different mean effective channel length from a flash EPROM produced in a different fabrication lot. This is so even though both flash EPROMs are of the same type. As noted above, these variations in effective channel length and mean effective channel length are due to process variations and other variations. The difference in the mean effective channel lengths of flash EPROMs typically causes the programming time to vary from flash EPROM to flash EPROM when the prior flash EPROMs with different effective channel lengths are programmed using the same programming voltages. The programming time of a floating gate flash EPROM cell varies inversely with respect to the drain programming voltage applied to the drain region of the cell during programming. FIG. 2B illustrates the relationship of the threshold voltage V.sub.t of memory cell 10 during programming with respect to the programming time and the programming drain voltage V.sub.D applied to memory cell 10. Memory cell 10 has a given programming ability in FIG. 2B.
In FIG. 2B, curve 23 is an illustration of the relationship between the threshold voltage and the programming time of cell 10 when the programming drain voltage V.sub.D is approximately 6 volts. Curve 24 illustrates the relationship between the threshold voltage and the programming time of cell 10 when the programming drain voltage V.sub.D is approximately 5 volts. As can be seen from FIG. 2B, if the programming drain voltage V.sub.D is relatively higher, the programming time for cell 10 to reach the same threshold voltage will accordingly be shorter when the programming ability of memory cell 10 remains the same.
FIG. 3 shows the circuitry of a prior drain programming voltage generation circuit 30 for generating a drain programming voltage for programming memory cells of a prior flash EPROM. Once drain programming voltage generation circuit 30 is fabricated, the drain programming voltage generated by circuit 30 cannot be adjusted to compensate for any variation in the effective channel length L.sub.eff of the prior flash EPROM.
Prior flash EPROMs typically include content addressable memory ("CAM") cells. The CAM cells are typically used to perform certain configuration and management functions. The CAM cells can be programmed to configure the flash EPROMs with respect to device operations. The CAM cells can also be used to activate (or deactivate) redundancy cells and reference cells with respect to the main memory array. The CAM cells are typically programmed with the configuration information before the flash EPROM reaches the end user as a final product.